Such chip antennas are also referred to as on-chip antennas. They are used, in particular, in wireless transmission systems that operate with millimeter waves up to the a terahertz range. An increasing number of applications can be found in the fields of radar, fast data transfer, imaging systems and sensors.
At the extremely high frequencies referred to above, electronics packaging technologies are more difficult and cost-intensive in comparison with antennas for lower frequencies. On the other hand, it is possible to integrate the antenna directly into the transceiver chip within a very small space and thus to simplify the packaging, because the wavelengths of the electromagnetic waves to be transmitted or received are shorter, which means that the antennas are small enough for on-chip integration.
One problem when embodying chip antennas is that silicon, which is used as a substrate in standard CMOS and BiCMOS processes, is a relatively poor support for antenna structures. The electrical impedance of silicon is relatively low, with signal losses ensuing as a result. In addition to that, the permittivity of silicon is relatively high, thus favoring the propagation of waves through the substrate. This causes the substrate to heat up, with scatter radiation being produced at the edges of the substrate. All this reduces the efficiency of chip antennas integrated on silicon substrates. Furthermore, when integrating chip antennas and electronic circuits on one and the same chip, substrate waves can transfer undesired signals to the electronic circuits and thus give rise to interference.
Various solutions for increasing the efficiency of chip antennas are known.
One approach is to thin the substrate to a specific thickness so that propagation of all wave modes up to mode TM0 is suppressed. This method works for GaAs as substrate material, but not for silicon substrates, due to the relatively low electrical impedance of silicon mentioned above, which causes corresponding signal losses.
Attempts have also been made to increase the electrical impedance of the silicon substrate near the antenna structure by means of proton implantation. However, this requires special technological equipment.
Removing the silicon under the conductor paths of the antenna structure with the aid of micromechanical technologies is known from the prior art. All that then supports the antenna structure is a thin membrane, which can easily break and cause the antenna to fall out.
One embodiment of a chip antenna which is accommodated along with a transceiver and a reflector in a semiconductor chip is described in patent specification U.S. Pat. No. 7,943,404. The emitter of the antenna is formed by structuring a metal level of a conductor path stack which is applied to the surface of the substrate during the “back end of line” (BEOL) stage of the production process. In order to improve the characteristics of the chip antenna, it is located in a region in which the electrical impedance of the substrate material has been increased by doping. To adapt the antenna to the desired frequency, the distance to a reflector located on the underside of the substrate is adjusted by thinning the substrate accordingly. Alternatively, or in combination with thinning, circular or elliptical trenches filled with a material having a lower dielectric constant may be located between the reflector and the emitter. This results in an average dielectric constant that is lower than that of the substrate. The disadvantage is that propagation of the waves along the surface of the substrate is not suppressed effectively, and that perforation of the substrate between the emitter and the reflector significantly reduces the mechanical stability of the chip.